UPDATED : 11 May 2007
Course Details ... Course content

Note: No more new/ spot Registrations for the event are accepted.

Five-day Course on
Digital VLSI Design

July 23-27, 2007
Golden Jubilee Hall, ECE Dept, Indian Institute of Science, Bangalore

Organized by

VLSI Society of India

http://vlsi-india.org/vsi/

Co-sponsored by IEEE-CAS Bangalore Chapter

http://ieee-cas-bangalore.org/

VLSI Society of India

http://vlsi-india.org/vsi/

 

Module – 1

3 Days – July 23-25, 2007

 

 

I. VLSI Implementations of Computer Arithmetic

David Harris

 

v      Number systems: Signed and unsigned integers, fixed point, floating point, carry-save representation, residue arithmetic

v      Addition: full adder design; CPAs: carry ripple, carry skip, carry look ahead, carry increment, tree adders, Ling adder; multi-input addition, CSAs

 

I. Circuit Design on the Back of an Envelope

David Harris

 

v      Delay Estimation

v      Logical Effort

v      Circuit Characterization

 

 

III. Low Power Circuit Design

Bharadwaj Amruthur

 

v      Leakage Reduction techniques

v      Power Gating Design Issues

v      Optimization of Sizing, Supply and Threshold for low power

 

IV. Low Power Memory Design

Bharadwaj Amruthur

 

v      Decoders

v      Sense amplifiers

v      Cell, Voltage Scaling

v      TCAM Basics

 

Registration

            Below is the tariff for Module-1 (July 23-25, 2007). Please refer registration details to attend both Module-1 and 2

 

MODULE-1 ( 3 Days )

Before July 1, 2007

After July 1, 2007

Professionals (Non-Members)

Rs. 8,000/-

Rs. 9,000/-

Professionals (VSI/ IEEE members)

Rs. 6,000/-

Rs. 7,000/-

Students/ Faculty (Non-members)

Rs. 5,000/-

Rs. 6,000/-

Students/ Faculty (VSI/ IEEE members)

Rs. 4,000/-

Rs. 5,000/-

 

Module – 2

2 Days – July 25-27, 2007

 

I. Advanced topics in VLSI Computer Arithmetic

David Harris

 

v      Multiplication: Word-serial, array multiplier, Wallace Trees, 4:2 trees, hybrid

v      Division: Word-serial, array divider, SRT division, division by multiplication

v      Floating Point: Addition, multiplication

v      Table approximations: Bipartite table lookup

 


II Advanced topics in Low Power Circuits

Bharadwaj Amruthur

 

v      Dynamic Voltage, Threshold and Frequency Scaling

v      Voltage Scaling of Memories


 

Registration
Below is the tariff for Module-2 (July 25-27, 2007). Please refer registration details to attend both Module-1 and 2
 

 

MODULE-2 ( 2 Days )

Before July 1, 2007

After July 1, 2007

Professionals (Non-Members)

Rs. 6,000/-

Rs. 7,000/-

Professionals (VSI/ IEEE members)

Rs. 5,000/-

Rs. 6,000/-

Students/ Faculty (Non-members)

Rs. 4,000/-

Rs. 5,000/-

Students/ Faculty (VSI/ IEEE members)

Rs. 3,000/-

Rs. 4,000/-

The course fee includes registration material, softcopy of notes, lunch and refreshments on all days.

Mode of Payment: Demand Draft, drawn in favor of  “VLSI Society of India” payable at Bangalore.

Please also register using the online registration form at http://vlsi-india.org/vsi/activities/reg.shtml apart from sending the filled hardcopy of registration form. Spot-registration subject to availability at the after deadline rates against DD or Cash.

Download Announcement with Registration Form. PDF 140KB

Course Details ... Course content
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