VLSI Education Day 2002
Advance Program
(Latest version available at http://vlsi-india.org)
August 29, 2002
Bangalore, India
Scope: To promote
applications and research related to all aspects of VLSI
In Cooperation With: VLSI
Society of India, IEEE Computer Society Technical Council on Test Technology
IEEE EDS/SSCS Bangalore Chapter
With
Support From: Texas Instruments, India, Indian Institute of Science
Venue: JN Tata
Auditorium, National Science Seminar Complex, Indian Institute of Science,
Bangalore
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8.00 AM – 9.00 AM |
Registration |
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9.00 AM – 9.15 AM |
Inauguration |
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9.15 AM – 10.45 AM |
Session E1: Keynote Talks M.J. Zarabi, Semiconductor Complex Ltd.,
Chandigarh. Perspectives on VLSI
Education and Industry in India. V.D. Agrawal, Agere Systems.
Interdisciplinary Computer Engineering curriculum. |
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10.45 AM – 11.15 AM |
Tea |
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Session E2: Industry-Academia Interaction Venue:
Room A |
Session E3: Project Management in the Curriculum Venue:
Room B |
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11.15
AM -- 12.15 AM |
S. Mahant-Shetti. KARMIC.
Integration Issues in Implementation of Student LSI-Design Projects. (Invited
Talk.) |
S. Ramesh. Texas Instruments
India. Project Management in VLSI
Design/EDA Organizations. (Invited Talk.) |
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Suresh Kumar. HP India. Software
Engineering Practices in Student Projects. (Invited Talk.) |
Anand Kasturi. Indian Institute of
Management. The New Recruits in an IT Company: A Behavioral Perspective. (Invited Talk.) |
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Session E4: Technology Venue:
Room A |
Session E5: The Verification Challenge Venue:
Room B |
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12.15
AM –1.15 PM |
N. Bhat, Indian Institute of Science.
CMOS Technology Issues in Mixed Signal Design. (Tutorial.) |
(R) B. A. Bhat, Synopsys India. Tackling Signal Integrity Issues during DSM Design. |
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(R)
A. Saha. Texas Instruments
India. Static Timing Analysis.
(Tutorial). |
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1.15
PM – 2.15 PM |
Lunch |
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2.15 PM – 3.45 PM |
Session E5: Frequently Not Asked Questions! Chair:
Nagi Subramanyam, Texas Instruments Experts from industry and academia will answer questions posed by
engineers and students on various aspects of VLSI Design/CAD. Questions may
be sent to ngs@india.ti.com |
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3.45 PM –4.15 PM |
Tea |
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4.45 PM – 6.15 PM |
Session E7: Future Growth of VLSI in India Moderator:
C.P. Ravikumar Panelists:
Prof. S. Srinivasan, IIT Madras, Prof. Dinesh Sharma, IIT Bombay, Prof. H.S. Jamadagni, IISc, Bangalore, Dr. H. Ramakrishna, Bharath Electronics Ltd. |
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6.15 PM – 7.00 PM |
Tea |
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7.00 PM – 8.00 PM |
Banquet Speech: Nitin
Deo, Magma Design Automation. Continuing Evolution of High Tech Economy: How Can India Arrive at
the Scene? |
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8.00 PM – 9.00 PM |
Banquet
Dinnner |
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VLSI Design and Test Workshops 2002
Advance Program
(Latest version available at http://vlsi-india.org)
August 30-31, 2002
Bangalore, India
Scope: To promote
applications and research related to all aspects of VLSI
In Cooperation With: VLSI
Society of India, IEEE Computer Society Technical Council on Test Technology
IEEE EDS/SSCS Bangalore Chapter
With
Support From: Texas Instruments, India, Indian Institute of Science
Venue: JN Tata
Auditorium, National Science Seminar Complex, Indian Institute of Science,
Bangalore
Advance Program for August 30, 2002 (Friday)
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Time |
Test Workshop |
High Level and Logic Design
Workshop |
Physical Design and VLSI Technology
Workshop |
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8:00 to 9:00 AM |
Registration
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9.00
- 10.00 AM |
Combined
with L1 |
Session L1: Verification C. Michael Chang, President and CEO, Verplex Systems Inc., and Harry
D. Foster, CTO, Verplex Systems Inc. Unifying Traditional and Formal Verification
through Property Specification. Invited Talk. |
Combined
with L1 |
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10.00 - 10.30 AM |
Tea |
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Session T1: SOC Verification & Test |
Session L2: VLSI Architecture I |
Session P1: Analog Design |
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10.30
- 12.30 PM |
(R) V. Dalal. Sasken Communications. System Level
Verification of Present Day System on a Chip (SOC) Designs. |
(R) A. D. Kishore and S. Srinivasan. IIT Madras. An Extended
Memory Architecture for Morphological Signal Processing. |
(R) S.C. Bose, A. Karmakar, Chadrashekhar & V. Sunitha,
CEERI Pilani, and V. Jain, G. Jain,
V. Kulshreshta & R. Mathew, BITS Pilani. Design, Synthesis, and
Physical Design of CMOS Operational Amplifier from User Specification. |
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(R) Satish Panigatti, Ambar Gadkari and Rubin Parekhji. Texas
Instruments India. Applying Model Checking for Verification of Small
Controllers. |
(R) D. Guha. Agilent Technologies India. Test and Interoperability
of an Optical Signal Processor using the concept of Transforms. |
(R) P. Admane, B. Viswanathan, S.R. Guruprasad and N. Garg. ControlNet India Pvt. Ltd., Goa. A Novel Approach to Unified RF
Frontend IC Design for Wireless Application. |
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(R) A. Saha and R. Ranmale. Texas Instruments India. Using
Formal Techniques for Identifying Uninitialized Registers in
SOC Designs. |
(R) T.S. Rajesh Kumar, Texas Instruments India, R. Govindarajan, Indian
Institute of Science, Manohar Sambandham, A and C.P. Ravikumar, Texas Instruments India. Memory Exploration
for Embedded Systems. |
(R) R. Srinivasan, C.Venkatesh and N. Bhat. Indian Institute of Science.
Comparative study of RF Tuned Amplifier Performance with Different
Inductor Configurations. |
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