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  2nd Workshop on Design Verification Methodologies
MARCH 24-25, 2006 - Wipro Technologies, Pune, India
Organized by VLSI Society of India
In co-operation with: IEEE Pune Sub Section
Speakers:
A. Vasudevan, Wipro Technologies, Raj Mitra, Texas Instruments, Muralidhar Bolisetty, Synopsys, Venkatesan Swaminathan, Intel, Deepali Maydeo, Tensilica, V. Kamakoti, IIT Madras, Subir K Roy, Texas Instruments, Shailesh Dave, eInfochips Ltd, Vinaya Singh, Cadence Design Systems, Mahesha Puttanna and Sunil Vishwanathan, Wipro Technologies and Amit Sharma, Synopsys.