EVENTS 2005 - PRESENT
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April 25-26, 2007 - PSG College of Technology, Coimbatore
Event details
Organized by: VLSI Society of India and PSG College of Technology, Coimbatore
Corporate Sponsors: Analog Devices India and Texas Instruments India
Speakers: Dr. P.V. Ananda Mohan, ECIL; Dr Shanthi Pavan, IIT Madras; Dr. Chetan D. Parikh, DA-IICT, Gandhinagar; Dr. M.C. Bhuvaneswari, PSG College of Technology; Dr. R. Neelaveni, PSG College of Technology; Jais Abraham, InnoDes Solutions Pvt Ltd; Jairam Sukumar, Texas Instruments India; Asif Ahmad, Analog Devices; Arjun Prakash, Tessolve Services Pvt Ltd; Sheetal Morajkar, Texas Instruments India Pvt Ltd; Girish Vaidya, Wipro Technologies
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The second workshop on Mixed Signal VLSI Design and Test was held at PSG College of Technology, Coimbatore, during 25th & 26th of April 2007. It was organized by the VLSI Society of India and the department of Electrical and Electronics Engg., PSG College of Technology. The corporate sponsors of the workshop were Analog Devices India and Texas Instruments India. The main objective of the workshop was to bring the industrial professionals and academicians together for a better appreciation of the challenges in the Mixed Signal Design and Test.
Dr Shanthi Pavan during his inaugural address Why does Low Voltage not imply Low Power In Analog VLSI? emphasized the need for the faculty and students to concentrate more on the fundamental subjects / concepts and the need of such workshops.His keynote talk addressed on how progressive scaling of power supply voltages has resulted in digital ICs with reduced power consumption. He also explained what low voltage operation means to the analog designer and why lower voltages do not necessarily imply lower power dissipation in analog circuits.
Mr. Asif Ahmad of Analog Devices in his talk entitled Design and Evaluation of A/D converters gave an overview of commonly used A/Ds such as SAR, Pipeline and Sigma Delta converters . He also emphasized on newly developed time interleaved architecture.
Mr. Arjun Prakash of Texas Instruments India in his talk on Analog Test in an SoC Device discussed the aspects of testing analog blocks, namely, power management circuits, analog filters and data converters. In her talk entitled Analysis and Design of CMOS Subcircuits.
Dr. R. Neelaveni focused on issues related to the design and analysis of sub circuits namely, Current Sources/ Sinks, Current Mirrors, Voltage and current references at the first level of design and amplifiers at the second level.
Dr. M C Bhuvanewari talked on Applications of Genetic Algorithms to Design of Operational Amplifiers that covered various evolutionary algorithms and how genetic algorithms can be applied the problem of CMOS operational amplifier design optimization. The Simulation results of GA applied to synthesis of a standard Miller OTA cell was also briefed in the workshop. |
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 Dr Shanthi Pavan during his inaugural address. |
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Dr. P.V. Ananda Mohan in his tutorial on Analog VLSI Filters, Switched Capacitor and Operational Transconductance Capacitor Filters covered the fundamentals of Analog Filter design for MOS VLSI. He stressed the importance of various issues such as need for tuning, programmability etc., A brief introduction to current-mode VLSI analog filters using devices such as Current conveyors, CFOA etc., was also discussed.
Mr.Jairam Sukumar in his talk on Design Planning for Mixed Signal SoCs reviewed the basics of noise generation and its propagation. He also described about design planning methodology and analysis methods for such scenarios.
Dr. Chetan D.Parikh`s talk Some Research Issues in Digital-to-Analog Converters focused on digital-to-analog converter (DAC) architectures, Methods to minimize glitches, SFDR, systematic and random errors in DACs. He also overviewed some of the current research and challenges in high-speed DAC architectures with an emphasis on current-steering DACs.
Mr.Jais Abraham’s talk on Test Challenges in the Nanometer Era briefed about the problems related to Nanometer test and described the solutions to these problems.
Mr.Girish Vaidya discussed about Mixed Signal Verification – Idea to Implementation, the need, approach and challenges in the mixed signal verification domain. He also covered some real-time case studies.
Mr. Anil Bhatnagar’s talk on How to Accelerate Mixed-Signal Verification using Fast-SPICE? emphasized on how to speed up mixed signal verification using Fast-SPICE simulation. High-level features of Fast-SPICE simulators were also discussed.
The panel discussion on Developing Analog and Mixed Signal Competency in India discussed the need for analog design talent in India, The skills needed for today and tomorrow, Challenges faced in developing talent in Analog Design and Industry-academia interaction in Analog/Mixed-signal design and test.
A total of 24 delegates attended the workshop. Most of them were faculty from engineering colleges, besides a few research scholars and professionals from industry. The feedback for the workshop was very good and the participants expressed the need for more such workshops, covering more on fundamental concepts. The speaker’s expertise and their involvement with the audience were highly appreciated. Dr. M C Bhuvaneswari coordinated the event and the organizing committee included Dr.P.Navaneethan, Ms.A.Sumathi, Mr.A.Natarajan, Mr.S.Karthikeyan and Mr.S.R.Sivarasu. Please contact VSI for the softcopy of workshop proceedings. |